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Preliminary Technical Data
FEATURES Pin Compatible 12 and 14 Bit DACs Serial Input, Voltage Output Maximum Output Voltage Range of 10V Data Readback 3 Wire Serial Interface Clear Function to a User Defined Voltage Power Down Function Serial Data Output for Daisy Chaining 16 Lead TSSOP Packages APPLICATIONS Industrial Automation Automatic Test Equipment Process Control General Purpose Instrumentation
Serial Input Voltage Output, 12/14 Bit DACs AD5530/AD5531
GENERAL DESCRIPTION
The AD5530 and AD5531 are single 12/14 bit serial input, voltage output DAC's respectively. They utilize a versatile three-wire interface that is compatible with SPITM, QSPITM, MICROWIRETM and DSP interface standards. Data is presented to the part in the format of a sixteen bit serial word. Serial data is available on the SDO pin for daisy chaing purposes. Data Readback allows the user to read the contents of the DAC register via the SDO pin. The DAC output is buffered by a gain of two amplifier and referenced to the potential at DUTGND. LDAC may be used to update the output of the DAC. A Power Down (PD) pin allows the DAC to be put into a low power state, and a CLR pin allows the output to be cleared to a user defined voltage, the potential at DUTGND. The AD5530 and AD5531 are available in 16 lead TSSOP packages.
FUNCTIONAL BLOCK DIAGRAM
VDD VSS
AD5530/AD5531
REFIN
R R +
12/14-BIT DAC
+ R R
VOUT
REFAGND
LDAC RBEN
DAC REGISTER
DUTGND
CLR
SDIN
SHIFT REGISTER
POWER-DOWN CONTROL LOGIC
PD
GND
SCLK
SYNC
SDO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
+15 10%; AD5530/AD5531-SPECIFICATIONS1(V ==220 pFV to GND, VAll = -15 V 10%;TGNDto=T0 V;, R = 5 k and C specifications unless otherDD SS L L MIN MAX
wise noted)
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient2 REFERENCE INPUTS 2 Reference Input Range DC Input Resistance Input Current DUTGND INPUT DC Input Impedance Max Input Current Input Range O/P CHARACTERISTICS Output Voltage Swing Short Circuit Current2 Resistive Load Capacitive Load DC Output Impedance2 DIGITAL I/O VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance2 SDO VOL Output Low Voltage POWER REQUIREMENTS VDD/VSS Power Supply Sensitivity Full Scale/V DD Full Scale/V SS IDD ISS
2
AD5530 12 1 1 2 2 1 20 40 0/5 100 1 60 0.3 -5/+5 10 15 5 220 0.5 2.4 0.8 10 10 0.4 +15/-15 110 100 2 2
AD5531 14 2 1 8 8 8 20 40 0/5 100 1 60 0.3 -5/+5 10 15 5 220 0.5 2.4 0.8 10 10 0.4 +15/-15 110 100 2 2
Units Bits LSB LSB LSB LSB LSB ppm ppm
Test Conditions/Comments
max max Guaranteed Monotonic Over Temperature max Typically within 1 LSB max Typically within 1 LSB typ FSR/C typ FSR/C max Max output range 10V Per Input. Typically 20 nA
V min/V max M typ A max k typ mA typ V min/V max V max mA max k min pF max max V min V max A max pF max V max V nom dB typ dB typ mA max mA max
Max output range 10V
To 0 V To 0 V
Total for All Pins ISINK = 1 mA 10% For Specified Performance
Outputs Unloaded. IDD in power down < 50A Outputs Unloaded.
NOTES 1 Temperature range for B Version: -40C to +85C. 2 Guaranteed by design. Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS1
(VDD = +10.8V to 16.5V, VSS = -10.8V to -16.5V; GND = 0 V; RL = 5 k and CL = 220 pF to GND, All specifications TMIN to TMAX, unless otherwise noted)
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Output Noise Spectral Density @ 1 kHz A 20 1.5 120 0.5 130 Units s typ V/s typ nV-s typ nV-s typ Test Conditions/Comments Full-Scale Change to 1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s DAC Latch Alternately Loaded with 0FFF Hex and 1000 Hex. Not Dependent on Load Conditions Effect of Input Bus Activity on DAC Output Under Test
nV/(Hz) 1/2typ All 1s Loaded to DAC.
NOTES 1 Specifications subject to change without notice. Guaranteed by design, not subject to production test.
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SPECIFICATIONS1 GND = 0 V; R = 5 k and C = 220 pF to GND, T (V = +12 V 10% ; V = -12 V 10%;
DD SS L L
A
1
= TMIN to TMAX, unless otherwise noted)
Test Conditions/Comments
AD5530/AD5531
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient2 REFERENCE INPUTS 2 Reference Input Range DC Input Resistance Input Current DUTGND INPUT DC Input Impedance Max Input Current Input Range O/P CHARACTERISTICS Output Voltage Swing Short Circuit Current2 Resistive Load Capacitive Load DC Output Impedance2 DIGITAL I/O VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance2 SDO VOL Output Low Voltage POWER REQUIREMENTS VDD/VSS Power Supply Sensitivity Full Scale/V DD Full Scale/V SS IDD ISS
2
AD5530 12 1 1 2 2 1 20 40 0/4.096 100 1 60 0.3 -5/+5 8.192 15 5 220 0.5 2.4 0.8 10 10 0.4 +12/-12 110 100 2 2
AD5531 14 2 1 8 8 8 20 40 0/4.096 100 1 60 0.3 -5/+5 8.192 15 5 220 0.5 2.4 0.8 10 10 0.4 +12/-12 110 100 2 2
Units Bits LSB LSB LSB LSB LSB ppm ppm
max max Guaranteed Monotonic Over Temperature max Typically within 1 LSB max Typically within 1 LSB typ FSR/C typ FSR/C max Max output range 8.192V Per Input. Typically 20 nA
V min/V max M typ A max k typ mA typ V min/V max V max mA max k min pF max max V min V max A max pF max V max V nom dB typ dB typ mA max mA max
Max output range 8.192V
To 0 V To 0 V
Total for All Pins ISINK = 1 mA 10% For Specified Performance
Outputs Unloaded. IDD in power down < 50A Outputs Unloaded.
NOTES 1 Temperature range for B Version: -40C to +85C. 2 Guaranteed by design. Specifications subject to change without notice.
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AD5530/AD5531
(VDD = +10.8V to 16.5V, VSS = -10.8V to -16.5V; GND = 0 V; RL = 5 k and CL = 220 pF to GND, All specifications TMIN to TMAX, unless otherwise noted)
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
1 2
STAND ALONE TIMING CHARACTERISTICS1,2
Limit at TMIN, TMAX 8 125 50 50 40 40 40 30 10 0 40 0 40 Units MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description SCLK Frequency SCLK cycle time SCLK low time SCLK high time SYNC to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Min SYNC high time Data setup time Data hold time SYNC high to LDAC low LDAC pulse width LDAC high to SYNC low CLR pulse width
Guaranteed by design. Not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
Specifications subject to change without notice.
t1 SCLK t4 t5 SYNC t6 MSB SDIN DB15 DB14 DB11 t7 t8 LSB DB0
t3
t2
t9 LDAC*
t 10
t 11
t 12 CLR
*LDAC may be tied permanently low if required.
Figure 1. Timing Diagram for Stand Alone Mode
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AD5530/AD5531
(VDD = +10.8V to 16.5V, VSS = -10.8V to -16.5V; VSS =-15 V 10%; GND = 0 V; RL = 5 k and CL = 220 pF to GND, All specifications TMIN to TMAX, unless otherwise noted)
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t8 t12 t13 t14 t15 t16 t17
1 2
DAISY CHAINING AND READBACK TIMING CHARACTERISTICS1,2,3
Limit at TMIN, TMAX 2 500 200 200 40 40 40 30 10 40 60 20 40 20 100 Units MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min ns min Description
SCLK Frequency SCLK cycle time SCLK low time SCLK high time SYNC to SCLK falling edge setup time SCLK falling edge to SYNC rising edge Min SYNC high time Data setup time Data hold time CLR pulse width SCLK Falling edge to SDO Valid SCLK Falling edge to SDO Invalid RBEN to SCLK falling edge setup time RBEN hold time RBEN falling edge to SDO valid
Guaranteed by design. Not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. 3SDO; R PULLUP = 5k, CL = 15pF. Specifications subject to change without notice.
t1 SCLK t4 t5 SYNC t7 MSB SDIN DB15 DB14 DB11 t8 LSB DB0 t 13
t3
t2
t 14 MSB LSB DB11 t 15 DB0 t 16 DB15
SDO (DAISY CHAINING)
RBEN t 17 SDO (READBACK) 0 MSB 0 t 13 RB13 t 14 RB0 LSB
Figure 2. Timing Diagram for Daisy Chaining and Readback
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AD5530/AD5531
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VDD to GND VSS to GND Digital Inputs to GND SDO to GND REFIN to REFAGND REFIN to GND REFAGND to GND DUTGND to GND Operating Temperature Range Industrial (B Version)
-0.3 V, +17 V +0.3 V, -17 V -0.3V to VDD +0.3 V -0.3V to +6.5 V -0.3V, +17 V VSS - 0.3V, VDD + 0.3V VSS - 0.3V, VDD + 0.3V VSS - 0.3V, VDD + 0.3V -40C to +85C
Storage Temperature Range -65C to +150C +150C Maximum Junction Temperature, (TJ max) Package Power Dissipation (TJ max - TA)/JA Thermal Impedance JA TSSOP(RU-16) 150.4C/W Lead Temperature (Soldering 10s) 300C IR Reflow, Peak Temperature 220C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD5530BRU AD5531BRU
Temperature Range -40 C to +85 C -40 C to +85 C
INL (LSBs) 1 2
DNL(LSBs) 1 1
Package Option* RU-16 RU-16
*RU = Thin Shrink Small Outline Package.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5530/5531 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION 16 Lead TSSOP
REFAGND 1 REFIN 2 LDAC 3 SDIN 4 SYNC 5 RBEN 6 SCLK 7 SDO 8 NC = NO CONNECT
16 VDD
AD5530/ AD5531
TOP VIEW (NOT TO SCALE)
15 V OUT 14 DUTGND 13 V SS 12 NC 11 GND 10 PD 9 CLR
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AD5530/AD5531
AD5530/AD5531 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description
1 2 3
REFAGND REFIN LDAC SDIN SYNC RBEN SCLK SDO
4 5 6 7 8
9
CLR PD GND NC VSS DUTGND VOUT VDD
10 11 12 13 14 15 16
For bipolar 10 V output range, this pin should be tied to 0V. This is the voltage reference input for the DAC. Connect to external +5V reference for specified bipolar 10 V output. Load DAC logic input (acitve low). When taken low, the contents of the shift register is transferred to the DAC register. LDAC may be tied permanently low enabling the outputs to be updated on the rising edge of SYNC. Serial data input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK. Logic Input signal used to frame the serial data input. Readback enable function. This function allows the contents of the DAC register to be read. Data from the DAC register will be shifted out on SDO pin on each rising edge of SCLK. Clock input. Data is clocked into the input register on the falling edge of SCLK. Serial Data out. This pin is used to clock out the serial data previously written to the input shift register or may be used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output, it should be pulled high with an external pull up resistor. In stand alone mode, SDO should be tied to GND or left high impedance. Level sensitive, active low input. A falling edge of CLR resets VOUT to DUTGND. The contents of the registers are untouched. When CLR is brought high again, the DAC output reverts to the original output as determined by the data in the DAC register. This allows the DAC to be put into a power down state. Ground reference. Do not connect anything to this pin. Negative analog supply voltage, -12 V 10% or -15 V 10% for specified performance. VOUT is referenced to the voltage applied to this pin. DAC output. Positive analog supply voltage, +12 V 10% or +15 V 10% for specified performance.
TERMINOLOGY Relative Accuracy
Output Voltage Settling time
Relative accuracy or endpoint linearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function.
Differential Nonlinearity
This is the amount of time it takes for the output to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Gain Error
Digital-to-Analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition.
Digital Feedthrough
Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the fullscale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Zero Scale Error
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
Zero code error is a measure of the output error when all 0s are loaded to the DAC latch.
Full Scale Error
This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF - 1 LSB.
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AD5530/AD5531 TYPICAL PERFORMANCE CHARACTERISTICS
TBD
TBD
TBD
Figure 3 . Typical INL Plot
Figure 4. Typical DNL Plot
Figure 5. Typical INL Error vs. Temperature
TBD
TBD
TBD
Figure 6. Typical DNL error vs. Temperature
Figure 7. Zero Scale and Full Scale Error vs. Temperature
Figure 8. Typical Digital to Analog Glitch Impulse
TBD
TBD
TBD
Figure 9. Settling Time
Figure 10. IDD, ISS vs. Temperature
Figure 11. Power On Reset
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AD5530/AD5531
GENERAL DESCRIPTION DAC Architecture
REFIN
The AD5530/AD5531 are pin compatible 12/14 bit DACs. The AD5530 consists of a straight 12 bit R-2R voltage mode DAC, while the AD5531 consists of a 14 bit R-2R section. Using a +5 V reference connected to the REFIN pin and REFAGND tied to 0V, a bipolar 10V voltage output results. The DAC coding is straight binary.
Serial Interface
12/14-BIT DAC 14
OUTPUT
LDAC
DAC REGISTER 14
SYNC
SYNC REGISTER 14
Serial data on the SDIN input is loaded to the input register under the control of SCLK, SYNC and LDAC. A write operation transfers a 16 bit word to the AD5530/ AD5531. Figure 1 and 2 show the timing diagrams. Figure 12 shows the contents of the input shift register. 12 or 14 bits of the serial word are data bits, the rest are don't cares. The serial word is framed by the signal, SYNC. After a high to low transition on SYNC, data is latched into the input shift register on the falling edges of SCLK. There are two ways in which the DAC register and output may be updated. The LDAC signal is examined on the falling edge of SYNC, depending on its status, either a synchronous or asynchronous update is selected. If LDAC is low, then the DAC register and output are updated on the low to high transition of SYNC. Alternatively, if LDAC is high upon sampling, the DAC register is not loaded with the new data on a rising edge of SYNC. The contents of the DAC register and the output voltage will be updated by bringing LDAC low any time after the 16 bit data transfer is complete. LDAC may be tied permanently low if required. A simplified diagram of the input loading circuitry is illustrated in Figure 13. Data written to the part via SDIN is available on the SDO pin 16 clocks later if the readback function is not used. SDO data is clocked out on the falling edge of the serial clock with some delay.
PD Function
SDIN
16 BIT SHIFT REGISTER
SDO
Figure 13. Simplified Serial Interface
READBACK Function
The AD5530/AD5531 allows the data contained in the DAC register to be read back if required. The pins involved are the RBEN and SDO (serial data out). RBEN is first asserted low, on the next falling edge of SCLK, while RBEN is still low, the contents of the DAC register are transferred to the shift register. RBEN may be used to frame the readback data by leaving it low for 16 clock cycles, or it may be asserted high after the required hold time. The shift register contains the DAC register data and this is shifted out on the SDO line on each falling edge of SCLK with some delay. This ensures the data on the serial data output pin is valid for the falling edge of the receiving part. The two MSBs of the 16-bit word will be `0's. The falling edge of CLR causes VOUT to be reset to the same potential as DUTGND. The contents of the registers remain unchanged, so the user can reload the previous data with LDAC after CLR is asserted high. Alternatively, if LDAC is tied low, the output will be loaded with the contents of the DAC register automatically after CLR is brought high.
CLR function
The PD pin down mode. a minimum, PD function register.
allows the user to place the device into power While in this mode, power consumption is at the device draws only 50A of current. The does not affect the contents of the DAC
DB15 (MSB)
DB0 (LSB) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1
X
X
D0
X
X
DATA BITS
Figure 12a. AD5530 Input Shift register contents
DB15 (MSB)
DB0 (LSB) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3
X
X
D2
D1
D0
DATA BITS
Figure 12b. AD5531 Input Shift register contents
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AD5530/AD5531
Output Voltage MICROPROCESSOR INTERFACING
The DAC transfer function is as follows VOUT = 2[2*(REFIN - REFAGND)*D / 2N + 2*RefAGND -REFIN ] - DUTGND where : D is the decimal data word loaded to the DAC register, N is the resolution of the DAC.
Bipolar Configuration
Microprocessor interfacing to the AD5530/AD5531 is via a serial bus that uses standard protocol compatible with microcontrollors and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal and a synchronization signal. The AD5530/AD5531 requires a 16-bit data word with data valid on the falling edge of SCLK. For all the interfaces, the DAC output update may be done automatically when all the data is clocked in or it may be done under the control of LDAC. The contents of the DAC register may be read using the Readback function. RBEN is used to frame the readback data which is clocked out on SDO. The following figures illustrate these DACs interfacing with a simple 4 wire interface. The serial interface of the AD5530/AD5531 may be operated from a minimum of three wires.
AD5530/AD5531 to ADSP-21xx
Figure 14 shows the AD5530/AD5531 in a bipolar circuit configuration. REFIN is driven by the AD586, +5V reference, while the REFAGND and DUTGND pins are tied to GND. This results in a bipolar output voltage ranging from -10 V to +10 V. Resistor R1 is provided (if required) for gain adjust. Figure 15 shows the transfer function of the DAC when REFAGND is tied to 0V.
+15V
2 6 8 C1 1 F AD586 5 4 R1 10k
V DD REFIN V OUT V OUT (-10V TO +10V)
AD5530/1*
DUTGND REFAGND V SS GND SIGNAL GND - 15V
An interface between the AD5530/AD5531 and the ADSP-21xx is shown in Figure 17. In the interface example shown, SPORT0 is used to transfer data to the DAC. The SPORT control register should be configured as follows : internal Clock operation, alternate framing mode; active low framing signal. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out of the DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the DAC. In the interface shown, the DAC output is updated using the LDAC pin via the DSP. Alternatively, the LDAC input could be tied permanently low and then the update takes place automatically when TFS is taken high.
ADSP-2101/ ADSP-2103*
SIGNAL GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. Bipolar +/-10 V operation.
2 REFIN
DAC OUTPUT VOLTAGE
FO
LDAC
AD5530/ AD5531*
0V
TFS
SYNC
DT
SDIN
SCLK
SCLK
-2 REFIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
DAC INPUT CODE
000 001
(3)FFF
Figure 16. AD5530/AD5531 to ADSP-21xx interface.
AD5530/AD5531 to 8051 Interface
Figure 15. Output Voltage vs. DAC input codes (Hex).
A serial interface between the AD5530/AD5531 and the 8051 is shown in Figure 16. TXD of the 8051 drives SCLK of the AD5530/AD5531, while RXD drives the serial data line, SDIN. P3.3 and P3.4 are bit programmable pins on the serial port and are used to drive SYNC and LDAC respectively. The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The user will have to ensure that the data in the SBUF register is arranged correctly as the DAC expects MSB first.
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AD5530/AD5531
APPLICATIONS
80C51/80L51* P3.4 LDAC
AD5530/ AD5531*
Optocoupler Interface
P3.3
SYNC
RXD
SDIN
TXD
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 17. AD5530/AD5531 to 8051 Interface.
When data is to be transmitted to the DAC, P3.3 is taken low. Data on RXD is clocked out of the microcontroller on the rising edge of TXD and is valid on the falling edge. As a result no glue logic is required between this DAC and microcontroller interface. The 8051 transmits data in 8-bit bytes with only 8 falling clock edges occurring in the transmit cycle. As the DAC expects a 16 bit word, P3.3 must be left low after the first eight bits are transferred. After the second byte has been transferred, the P3.3 line is taken high. The DAC may be updated using LDAC via P3.4 of the 8051.
AD5530/AD5531 to MC68HC11 Interface
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3kV. The serial loading structure of the AD5530/AD5531 makes it ideal for opto-isolated interfaces as the number of interface lines is kept to a minimum. Figure 19 shows a 4 channel isolated interface to the AD5530/AD5531. To reduce the number of optoisolators, if the simultaneous updating of the DAC is not required, then the LDAC pin may be tied permanently low.
VCC
CONTROLLER CONTROL OUT SYNC OUT SERIAL CLOCK OUT SERIAL DATA OUT TO LDAC TO SYNC TO SCLK TO SDIN
Figure 18 shows an example of a serial interface between the AD5530/AD5531 and the MC68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC, while the MOSI output drives the serial data lines, SDIN. SYNC is driven from one of the port lines, in this case PC7.
MC68HC11* PC6 PC7 MOSI SCK LDAC SYNC SDIN SCLK
OPTO-COUPLER
Figure 19. Opto-Isolated Interface.
Serial Interface to Multiple AD5530s or AD5531s
AD5530/ AD5531*
Figure 20 shows how the SYNC pin is used to address multiple AD5530/AD5531s. All devices receive the same serial clock and serial data, but only one device will receive the SYNC signal at any one time. The DAC addressed will be determined by the decoder. There will be some feedthrough from the digital input lines, the effects of which can be minimized by using a burst clock.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 18. AD5530/AD5531 to MC68HC11 interface.
The 68HC11 is configured for master mode; MSTR=1, CPOL=0 and CPHA = 1. When data is transferred to the part, PC7 is taken low, data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight falling clock edges occur in the transmit cycle, so in order to load the required 16 bit word, PC7 is not brought high until the second eight bit word has been transferred to the DACs input shift register. LDAC is controlled by the PC6 port output. The DAC can be updated after each two byte transfer by bringing LDAC low. This example does not show other serial lines for the DAC. If CLR were used, it could be controlled by port output PC5. In order to read data back from the DAC register, the SDO line could be connected to MISO of the MC68HC11, with RBEN tied to another port output controlling and framing the readback data transfer.
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AD5530/AD5531
AD5530/AD5531* SCLK SYNC SDIN VCC SDIN SCLK VOUT
ENABLE CODED ADDRESS
EN DECODER*
AD5530/AD5531* SYNC SDIN SCLK DGND AD5530/AD5531* SYNC VOUT VOUT
*ADDITIONAL PINS OMITTED FOR CLARITY
SDIN SCLK
AD5530/AD5531* SYNC SDIN SCLK VOUT
Figure 20. Addressing Multiple AD5530/AD5531s.
Daisy Chaining Interface with Multiple AD5530s or AD5531s
A number of these DAC parts may be daisy chained together using the SDO pin. Figure 21 illustrates such a configuration.
V DD R SCLK AD5530/1* SDIN SDO
R SCLK SCLK AD5530/1* SDIN SDIN SDO SCLK AD5530/1* SDIN SDO
R
SYNC
SYNC
SYNC
SYNC
TO OTHER SERIAL DEVICES
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 27. Daisy Chaining Multiple AD5530/1s.
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AD5530/AD5531
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
1 8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.246 (6.25)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
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